Technical Presentations

Technical Presentations
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Infineon
	Semiconductor Development Trends - Implications for 3D Integration
KAIST
	Wafer Level Package Using Pre-Applied Anisotropic Conductive Films (ACFs) for Flip-Chip Interconnections
NXP
	High-Value Trench Decoupling Capacitors for 3D SiP Applications
	Through-Wafer Interconnect Technology Options for 3D SiP
Qimonda
	3D Integration by Thru-Silicon-Via Stacking Requirements and Trends: A view from memory
Rohm & Haas
	Advances in Wafer Plating: The Next Challenge: Through Silicon Via Platings